In certain applications, engineers may wish to simulate a system, e.g., a communication system, prior to constructing the actual system. Simulations may allow engineers to model aspects of the communication system before expending time, money, and other resources to actually construct the system. For example, an engineer may use a computing environment to create a model for the communication system that includes array, matrix, and/or vector formulations. The engineer may attempt to execute the model on a hardware resource (e.g., a central processing unit (CPU), a graphical processing unit (GPU), a field-programmable gate array (FPGA), etc.). The model may utilize data (e.g., arbitrary vector size data, arbitrary matrix size data, etc.) to execute on the hardware resource.
During model execution, the computing environment may attempt to execute the model more quickly on the hardware resource by batching the data together and by sending the batched data together to the hardware resource for execution. However, the hardware resource may not be able to handle the batched data due to limited resources (e.g., limited buffer sizes). Increasing the hardware resources during execution of the model may not be feasible.
In such a situation, the computing environment is unable to provide arbitrary size data to one or more hardware resources for execution, without recompiling and/or re-synthesizing the model. Furthermore, recompiling and/or re-synthesizing the model are time consuming and expensive processes.